1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a memory device capable of preventing malfunction that may be caused by noise resulting from variation in the output signal of an output buffer circuit.
2. Background of the Invention
FIG. 5 is a circuit block diagram schematically showing the circuit configuration of a conventional semiconductor memory device a, which includes an address terminal Ta for receiving an address signal, a control signal, an inverter circuit INV1 serving as an address input buffer circuit to receive an address signal and feeding its output to a peripheral circuit b, and another inverter INV2 serving as an input buffer circuit to receive a control signal and feeding its output to a control circuit c.
There are also shown a memory cell group d, a sense amplifier e for amplifying storage data read out from the memory cell, and an output buffer circuit f for receiving the output signal of the sense amplifier e. The buffer circuit f comprises a CMOS inverter consisting of a P-channel MOS FET Ma and an N-channel MOS FET Mb, inverters INV3 and INV4 forming input circuits thereto, a nor circuit NOR, a nand circuit NAND and an inverter INV5. Denoted by To is an output terminal of the output buffer circuit f.
The nand circuit NAND receives at its one input terminal an OE (output enable) signal from the control circuit c while receiving at its other input terminal a data signal from the sense amplifier e. The nr circuit NOR receives at its one input terminal a signal obtained by inverting the OE signal of the control circuit c through the inverter INV5 while receiving at its other input terminal the data signal from the sense amplifier e. The output signal of the nor circuit NOR is inverted through the inverter INV3 and then is applied to the gate of the P-channel MOS FET Ma, while the output signal of the nand circuit NAND is inverted through the inverter INV4 and then is applied to the gate of the N-channel MOS FET Mb. To the output terminal To of the memory is connected a TTL or similar logic circuit. Denoted by Cl is the capacity of a load.
There are further included a power terminal Tv of the memory a and a ground terminal Tg thereof, wherein a supply voltage Vcc of, for example, 6 V is applied between the power terminal Tv and the ground terminal Tg.
Also shown are an inductance ls (10 nH) resulting from a socket of the memory a, an inductance lv (30 nH) existing on the ground side due to the ground lead frame and bonding wire. The existence of such inductances brings about a great problem, which will be described later in detail.
The present inventor proposed an improved circuit configuration previously, as disclosed in Japanese Patent Laid-open No. 61 (1986)-108223, wherein one of drive transistors in the final stage of an output buffer circuit is connected to a diode merely for a predetermined period of time and then is switched over to a conventional connection by the use of a delay circuit to consequently reduce current noise.
In the semiconductor memory a shown in FIG. 5, noise is generated in the ground line of power supply line by the operation of the output buffer circuit f and causes malfunction of the inverter circuit INV1 to induce an address variation, which eventually varies the output signal of the output buffer circuit f. This problem will now be described below more specifically. In the output buffer circuit f supplied with a voltage Vcc of 6 V, its "high" output voltage is 6 V while its "low" output voltage is 0 V. In contrast to 3 V, which is one half of the supply voltage Vcc, generally a TTL circuit connected to the output side of the semiconductor memory a has a logic threshold voltage of 1.5 V. Therefore, the output voltage of the output buffer circuit f turns from "low" to "high" when rising about 1.5 V from 0 V. Meanwhile the output voltage of the output buffer circuit f turns from "high" to "low" when falling below 1.5 V after a drop of 4.5 V from 6 V. Thus, the time required for obtaining a readable state is prone to be longer in the case of a voltage change from "high" to "low". In order to raise the reading speed by minimizing such required time, it is necessary to enhance the driving capability of the MOS FET Mb for increasing the discharge current of the load capacity Cl to cause fast discharge. Particularly when the ports connected to the output buffer circuit f are numerically great, it is necessary to increase the discharge current. However, if such discharge is executed fast, a counterelectromotive force is generated due to the aforementioned parasitic inductances lg and ls, so that the ground line comes to have a level higher than the intrinsic ground leveI by a value corresponding to the counterelectromotive force. And such higher-level voltage appears in the form of noise having an amplitude of 2 V or so as shown by a solid line in FIG. 6. This noise exerts considerable effect on the operation of the inverter circuit INV1 because of the following reason. A "high" voltage VINL of the address signal is 2.2 V (while a "low" voltage VINL of the input address signal is 0.8 V). And the former stage of the memory a consisting of a TTL circuit similarly to the latter stage needs to be capable of processing the input address signal of 2.2 V as a "high" signal. However, since the aforementioned counterelectromotive force causes a transient state where a noise source is inserted between the intrinsic ground and the ground in the semiconductor memory a, the address signal of 2.2 V is received and processed as a "low" signal. That is, even when the potential at the gate of an unshown groundside MOS FET in the inverter circuit INV1 is 2.2 V, its source potential actually reaches 2 V or so due to the noise and further there exists a threshold voltage of IV or more of the MOS FET itself, so that the gate-source voltage becomes lower than the threshold voltage and therefore it fails to conduct when conduction is necessary. Consequently the output voltage of the inverter INV1 comes to exceed the logic threshold level of the next-stage circuit due to the noise as shown by a one-dot chain line in FIG. 6. As a result, the level of the next-stage circuit, of which "high" output voltage should be 6 V, falls to the vicinity of 0 V as shown by a broken line in FIG. 6. Such noise is termed current noise which causes transient malfunction of the inverter INV1. This signifies that an address variation is induced by the noise. And the read data content is rendered different by such address variation to eventually bring about transient malfunction of the output buffer circuit f as well. Accordingly, there may occur a phenomenon of oscillation as represented by broken lines in FIG. 8.
Assuming now that there is no problem of such current noise, in case the level of the read data signal Data turns from "low" to "high" as shown by a solid line in FIG. 8, the output signal Out of the output buffer circuit f also turns to a "low" level in response thereto as shown by the solid line. And thereafter the read data signal Data and the output signal Out of the output buffer circuit f are supposed to remain unchanged until a different address is accessed and the content of the read data signal Data is changed.
However, when the output signal Out is changed by a change in the read data signal Data (change not relevant to malfunction), the aforementioned current noise is generated by such change in the output signal Out to consequently bring about malfunction that the address is temporarily varied. And such temporary address variation causes a change of the read data signal Data as shown by a broken line. Then the output signal Out is also change correspondingly to generate current noise, which brings about a temporary address variation to eventually change the read data signal Data as well. Thus, as mentioned above, there occurs a phenomenon of oscillation shown by a broken line in FIG. 8.
Upon variation of the address signal due to generation of the current noise, an equalizing address transition pulse is produced to perform equalization so that, during reading the output signal Out, a transiently unstable state is induced by the equalization resulting from generation of the address transition pulse, whereby reading the signal may be rendered impossible.
Such current noise is generated not only when discharging the load capacity Cl but also when charging the same, i.e. at the rise of the output voltage from "low" to "high".
The malfunction described above can be eliminated by preventing generation of current noise. However, in the case of a high-speed static RAM (SRAM) or the like, the speed of discharging or charging the load capacity Cl needs to be increased to enhance the driving capability of the output buffer circuit, whereby generation of current noise is rendered unavoidable.